The present invention relates to a digital logic circuit, and more particularly, to a digital logic circuit to be realized as a monolithic integrated circuit.
As is well known, accompanying progress in large scale integrated circuit (hereinafter referred to as LSI) of digital logic circuits, the number of internal nodes therein has been greatly increased, and especially where the circuit contains memory elements (flip-flops or the like), the entire testing of such LSI has become extremely difficult.
For overcoming this difficulty, a method, so-called scan-path method for simplifying the test by converting a general sequential logic circuit comprised in the circuit into a combinational logic circuit has been known, in which flip-flops are arranged at particular portions within a logic circuit to divide them into a number of groups so that each flip-flop group may be independently operated as a shift register upon a test operation mode which is different from a normal operation mode, and at any arbitrary time point the state of any arbitrary flip-flop can be read or rewritten by connecting test terminals to the clock input, data input, data output, etc. of the flip-flop group. While this method is surely very effective for simplifying the method for testing an LSI, its shortcoming exists in that test input and output terminals therefore are greatly increased in number. Though this shortcoming is not remarkable in the case where a large scale logic circuit is constructed according to the conventional system which uses as a basic unit a printed circuit card having integrated circuits of small scale integration mounted thereon and having a large number of connector terminals, it is becoming extremely disadvantageous at present because, accompanying the increase of a degree of integration of integrated circuit, there remains no margin for additional terminals.